This invention relates to a semiconductor device having a retrograde well structure and a method of manufacturing thereof.
In an integrated circuit for memory retention such as a DRAM, and so forth, a so-called soft error may arise wherein information stored in the integrated circuit is accidentally lost. A typical cause of soft error is an xcex1-ray.
For example, when a memory element comprising a NMOSFET is formed on a p type semiconductor substrate, if the xcex1-ray enters the p type semiconductor substrate, the xcex1-ray interacts with an atom in the p type semiconductor substrate, energy in the xcex1-ray is lost, and the xcex1-ray slows down. Many electron-hole pairs are produced in the above process. An electron as a minority carrier in the produced electron-hole pairs reaches an n type diffusion layer, and stored information (potential) in the memory element is reversed.
Further, in a CMOS structure, a parastic PNP bipolar transistor, which comprises a source/drain of a PMOS, a N-well, and a p-well and a parastic NPN bipolar transistor which comprises a source/drain of a NMOS, a p-well, and a n-well continuously arranged, establishes a thyristor. As a result, current flows between power supply terminals or the like in the CMOS circuit, and a so-called latch up phenomenon is easily caused. When the impurity concentration of the well is low, latch-up easily occurs, because resistance at the time current flows into the well becomes high, and voltage drop becomes large. If latch up occurs, circuit performance is checked, according to circumstance, and an integrated circuit containing the latch up will be destroyed.
As a means for solving the above problem, an impurity concentration of the bottom of a well is increased, such that a so-called retrograde well structure is adopted. In this manner, the impurity is implanted in a semiconductor substrate with high energy by ion implantation. Almost all retrograde well structures are formed by the means.
The retrograde well structure and a method of manufacturing it based on the above means are disclosed in K. Tsukamoto et al., xe2x80x9cHigh energy iron Implantation for ULSIxe2x80x9d Nucl. Instr. and Meth., pp. 584-591, 1991, for example.
FIG. 77 shows a sectional view of a semiconductor device of a CMOS structure forming a retrograde well. The semiconductor device includes a p type semiconductor substrate 101; a retrograde p well 103; a retrograde n well 104; an field oxide film 124; a source/drain 125; a gate oxide film 126; and a gate electrode 127. FIG. 78 shows an impurity density distribution of the depth direction in a substrate section of a X-Xxe2x80x2 cross-section of the semiconductor device in FIG. 77. FIG. 79 shows an internal potential in the X-Xxe2x80x2 cross-section.
As shown in FIGS. 77-79, in the retrograde p well 103, an impurity is implanted by high energy ion implantation, and a peak of the impurity concentration can be formed at the depth desired in the substrate. Consequently when a transistor of a CMOS structure on the retrograde p well 103 is formed, resistance is controlled and voltage drop becomes small in a high concentration part of the bottom of the retrograde p well 103. Therefore common emitter current gain of a parasitic bipolar transistor is minimized, and latch up does not easily occur.
Further, when a memory cell is formed on the retrograde p well 103 instead of the CMOS structure, electrons, which are minority carriers, are interrupted before reaching the source/drain 125 by a potential barrier generated from a difference in Fermi level between the peak of the impurity concentration of the bottom of the retrograde p well 103 and a substrate impurity region, whereby soft error resistance is improved.
Furthermore, improvement of soft error resistance is disclosed in Japanese Patent Application Laid-Open No. 212453/1992. In the Japanese Patent Application Laid-Open, describing an impurity structure of a semiconductor substrate and a method of manufacturing, it is stated that an n type impurity layer surrounds a retrograde p well.
FIG. 80 shows a sectional view of a part of a substrate of a semiconductor device. The semiconductor device includes an n type impurity layer 105 surrounding the retrograde p well 103. A NMOS is formed on the retrograde p well 103, and a memory region is formed. FIG. 81 shows an impurity density distribution of the depth direction in a Y-Yxe2x80x2 cross-section of the semiconductor device in FIG. 80.
According to this structure, minority carriers are generated by an xcex1-ray or the like, that is, electrons are absorbed by the n type impurity layer 105. Therefore, electron flow is interrupted before reaching a source/drain layer (not shown) formed on a surface of the retrograde p well 103, and soft error resistance is improved.
To improve latch up resistance, there is a structure forming a low concentration well on a surface of a semiconductor substrate having a very high impurity concentration. The structure is disclosed in F. S. Lai et al., xe2x80x9cA Highly latch up-immune 1 xcexcm CMOS technology fabricated with 1 Mev ion implantation and self-aligned TiSi2xe2x80x9d IEDM Tech. Dig., pp. 513-516, 1985, for example.
FIG. 82 shows a sectional view of a part of a substrate of a semiconductor device. The semiconductor device includes an impurity layer which is formed on a surface of the substrate having a very high p type impurity concentration. The semiconductor device includes a retrograde n well 104; a high concentration p type substrate 106; and a p well 113. A PMOS is formed on the retrograde n well 104. A NMOS formed on the p well 113. The CMOS is formed by the PMOS and the NMOS. FIG. 83 shows an impurity density distribution of the depth direction in a Z-Zxe2x80x2 cross-section of the semiconductor device in FIG. 82.
In the semiconductor device, according to using the high concentration p type substrate 106, substrate resistance is reduced, voltage drop produced by current in the substrate becomes small, and a latch up phenomenon of the CMOS circuit can be controlled.
However, as integrated circuits are reduced in size, soft error resistance and latch up resistance both fall in the conventional retrograde well structure. Further, when an impurity structure is produced by an n type impurity layer surrounding a retrograde p well, a semiconductor device needs a terminal for potential of the N type impurity layer as a middle layer. Therefore, complexity of a structure increases.
Furthermore, it is possible to manufacture of an integrated circuit having a memory element and a calculation circuit of a high density being formed on the same chip by advanced circuit design and processing. However, in the integrated circuit, high soft error resistance and high latch up resistance are required at the same time.
Therefore, when a structure having a low impurity concentration surface layer formed on a high impurity concentration substrate is used, the structure is effective in a CMOS structure, because high latch up resistance can be obtained. However, the structure is not effective for improvement of soft error resistance. Conversely, a potential barrier is formed by a difference in Fermi level between the two layers, diffusion of minority carriers into the substrate is interrupted by the potential barrier, and the minority carrier is diffused into an element formation region. As a result, soft error resistance is degraded.
Accordingly, one object of the present invention is to provide a semiconductor device having a substrate impurity structure that has both soft error resistance and latch up resistance and that prevents faulty circuit operation when the semiconductor device is formed with a fine structure.
Another object of this invention is to provide a method of manufacturing the semiconductor device.
These and other objects and advantages are achieved by providing a new and improved semiconductor device including a semiconductor substrate of a first conductivity type and having a first impurity concentration. A retrograde well of the first conductivity type and having a second impurity concentration with an impurity concentration peak is formed in a main surface of the semiconductor substrate. A first impurity layer of a third impurity concentration comes into contact with the underside of the retrograde well. The third impurity concentration is smaller than the impurity concentration peak of the first impurity concentration and a concentration peak of the second impurity concentration. Finally, an element is formed on the first impurity layer.
The present invention also provides a semiconductor device including a semiconductor substrate of a first conductivity type and having a first impurity concentration. A first impurity layer of the first conductivity type and having a second impurity concentration with an impurity concentration peak smaller than the first impurity concentration is formed in a main surface of the semiconductor substrate. A second impurity layer of a second conductivity type and having a third impurity concentration with an impurity concentration peak smaller than the first impurity concentration comes into contact with the underside of the first impurity layer. Finally, a MOS transistor is formed on the first impurity layer.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawing. It is to be expressly understood, however, that the drawing is for purpose of illustration only and is not intended as a definition of the limits of the invention.